MARC details
000 -LEADER |
fixed length control field |
01702nam a2200421 a 4500 |
001 - CONTROL NUMBER |
control field |
BDZ0005922751 |
003 - CONTROL NUMBER IDENTIFIER |
control field |
StDuBDS |
005 - DATE AND TIME OF LATEST TRANSACTION |
control field |
20201215154328.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
030826s2004 enka f b 001|0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9780130399854: |
Terms of availability |
£34.99 |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
013039985X (pbk.) : |
Terms of availability |
£34.99 |
040 ## - CATALOGING SOURCE |
Original cataloging agency |
StDuBDS |
Language of cataloging |
eng |
Transcribing agency |
StDuBDS |
Modifying agency |
StDuBDSZ |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
COM |
Source |
ukslc |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
TJ |
Source |
thema |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
TBD |
Source |
thema |
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
621.381 |
100 1# - MAIN ENTRY--PERSONAL NAME |
Personal name |
Zwolinski, Mark. |
9 (RLIN) |
84348 |
245 10 - TITLE STATEMENT |
Title |
Digital system design with VHDL / |
Statement of responsibility, etc. |
Mark Zwoliński. |
250 ## - EDITION STATEMENT |
Edition statement |
2nd ed. |
260 ## - PUBLICATION, DISTRIBUTION, ETC. |
Place of publication, distribution, etc. |
Harlow : |
Name of publisher, distributor, etc. |
Pearson Education, |
Date of publication, distribution, etc. |
2004. |
300 ## - PHYSICAL DESCRIPTION |
Extent |
xiii, 368 p. : |
Other physical details |
ill. ; |
Dimensions |
24 cm. |
500 ## - GENERAL NOTE |
General note |
CW508 |
500 ## - GENERAL NOTE |
General note |
Previous ed.: 2000. |
504 ## - BIBLIOGRAPHY, ETC. NOTE |
Bibliography, etc. note |
Includes bibliographical references (p. 339-340) and index. |
505 ## - FORMATTED CONTENTS NOTE |
Formatted contents note |
Introduction -- Combinational logic design -- Combinational logic using VHDL gate models -- Combinational building blocks --Synchronous sequential design -- Models of sequential logic blocks -- Complex sequential systems -- VHDL simulation -- VHDL synthesis -- Testing digital systems -- Design for testability -- asychronous sequential design -- Interfacing with the analogue world. |
590 ## - LOCAL NOTE (RLIN) |
a |
52.76 |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Digital electronics |
General subdivision |
Data processing |
9 (RLIN) |
84349 |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
VHDL (Computer hardware description language) |
9 (RLIN) |
9139 |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Electronic digital computers |
General subdivision |
Circuits |
9 (RLIN) |
3255 |
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Computers and IT. |
Source of heading or term |
ukslc |
9 (RLIN) |
31801 |
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Electronics & communications engineering |
Source of heading or term |
thema |
9 (RLIN) |
84350 |
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Technical design |
Source of heading or term |
thema |
9 (RLIN) |
31529 |
902 ## - LOCAL DATA ELEMENT B, LDB (RLIN) |
a |
170313 |
907 ## - LOCAL DATA ELEMENT G, LDG (RLIN) |
a |
.b10269721 |
b |
cgen |
c |
- |
942 ## - ADDED ENTRY ELEMENTS (KOHA) |
Suppress in OPAC |
0 |
998 ## - LOCAL CONTROL INFORMATION (RLIN) |
Operator's initials, OID (RLIN) |
0 |
Cataloger's initials, CIN (RLIN) |
060126 |
First Date, FD (RLIN) |
m |
Local |
a |
-- |
- |
-- |
0 |