MARC details
000 -LEADER |
fixed length control field |
03302nam a2200469 a 4500 |
001 - CONTROL NUMBER |
control field |
BDZ0007894715 |
003 - CONTROL NUMBER IDENTIFIER |
control field |
StDuBDS |
005 - DATE AND TIME OF LATEST TRANSACTION |
control field |
20190531155630.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
070802s2008 ne a f b 001 0 eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9780123705228: |
Terms of availability |
£44.99 |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
0123705223 |
040 ## - CATALOGING SOURCE |
Original cataloging agency |
StDuBDS |
Transcribing agency |
StDuBDS |
Modifying agency |
StDuBDSZ |
050 #0 - LIBRARY OF CONGRESS CALL NUMBER |
Item number |
R43 2008 |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
COM |
Source |
ukslc |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
TJF |
Source |
thema |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
UK |
Source |
thema |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
UYF |
Source |
thema |
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
621.395 |
245 00 - TITLE STATEMENT |
Title |
Reconfigurable computing : |
Remainder of title |
the theory and practice of FPGA-based computation / |
Statement of responsibility, etc. |
edited by Scott Hauck and André DeHon. |
260 ## - PUBLICATION, DISTRIBUTION, ETC. |
Place of publication, distribution, etc. |
Amsterdam ; |
-- |
London : |
Name of publisher, distributor, etc. |
Morgan Kaufmann, |
Date of publication, distribution, etc. |
2008. |
300 ## - PHYSICAL DESCRIPTION |
Extent |
xxix, 908 p. : |
Other physical details |
ill. ; |
Dimensions |
24 cm. |
490 #0 - SERIES STATEMENT |
Series statement |
Systems on silicon |
504 ## - BIBLIOGRAPHY, ETC. NOTE |
Bibliography, etc. note |
Includes bibliographical references and index. |
505 ## - FORMATTED CONTENTS NOTE |
Formatted contents note |
[Part One: Reconfigurable Computing Hardware] Chapter 1 - Device Architecture -- Chapter 2 - Reconfigurable Computing Devices -- Chapter 3 - Reconfigurable Computing Systems -- Chapter 4 - Reconfiguration Management |
505 ## - FORMATTED CONTENTS NOTE |
Formatted contents note |
[Part Two: Software] Part II Intro -- Chapter 5 - Computer Models and System Architectures André DeHon -- Chapter 6 - Hardware Description Languages (VHDL) -- Chapter 7 - Compilation for Reconfigurable Computing Machines -- Chapter 8 - Streaming Models 8.1 MATLAB/SIMULINK 8.2 SCORE -- Chapter 9 SIMD/Vector -- Chapter 10 - OS/Runtime Systems -- Chapter 11 - JHDL -- Chapter 12 -Technology Mapping -- Chapter 13 - Placement 13.1 General-purpose / FPGA 13.2 Datapath 13.3 Constructive -- Chapter 14 - Routing -- Chapter 15 - Retimin -- Chapter 16 - Bitstream Generation, JBits -- Chapter 17 - Fast Mapping |
505 ## - FORMATTED CONTENTS NOTE |
Formatted contents note |
[Part Three: Application Development] PART III INTRO -- Chapter 18 - Evaluating and Optimizing problems for FPGA implementations -- Chapter 19- Instance-specific design, Constant Propagation & Partial Evaluation -- Chapter 20 - Precision Analysis & Floating Point -- Chapter 21 - Distributed Arithmetic -- Chapter 22 - CORDIC -- Chapter 23 - Task allocation: FPGA vs. CPU partitioning |
505 ## - FORMATTED CONTENTS NOTE |
Formatted contents note |
[PART Four: Case Studies] Chapter 24 - Image Processing, Variable Precision, Algorithm Alteration: SPIHT Compression -- Chapter 25 - Run-time reconfiguration: Automatic Target Recognition -- Chapter 26 - Problem-specific circuitry: SAT Solving -- Chapter 27 - Multi-FPGA Systems: Logic Emulation -- Chapter 28- Floating Point -- Chapter 29 - FDTD -- Chapter 30 - Genetic Evolution -- Chapter 31 - Packet Filtering (Networking application) -- Chapter 32 - Active Pages [Memory centric] |
505 ## - FORMATTED CONTENTS NOTE |
Formatted contents note |
[Part Five: Theoretical Underpinnings and Future Directions] PART V INTRO Chapter 33- Theoretical Underpinnings, Metrics and Analysis -- Chapter 34 - Defect and Fault Tolerance -- Chapter 35 - Reconfigurable Computing and Nanotechnology |
590 ## - LOCAL NOTE (RLIN) |
a |
58.49 |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Field programmable gate arrays. |
9 (RLIN) |
9499 |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Adaptive computing systems. |
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Computers and IT. |
Source of heading or term |
ukslc |
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Electronics engineering |
Source of heading or term |
thema |
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Computer hardware |
Source of heading or term |
thema |
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Computer architecture & logic design |
Source of heading or term |
thema |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
DeHon, André. |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Hauck, Scott. |
902 ## - LOCAL DATA ELEMENT B, LDB (RLIN) |
a |
140901 |
907 ## - LOCAL DATA ELEMENT G, LDG (RLIN) |
a |
.b1032818x |
b |
cgen |
c |
- |
942 ## - ADDED ENTRY ELEMENTS (KOHA) |
Suppress in OPAC |
0 |
998 ## - LOCAL CONTROL INFORMATION (RLIN) |
Operator's initials, OID (RLIN) |
0 |
Cataloger's initials, CIN (RLIN) |
080512 |
First Date, FD (RLIN) |
- |
Local |
a |
-- |
- |
-- |
0 |