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Rapid prototyping of digital systems / James O. Hamblen, Tyson S. Hall, Michael D. Furman.

By: Contributor(s): Material type: TextTextPublication details: New York : Springer, 2006.Edition: Quartus II edDescription: xvi, 371 p. : ill. ; 26 cm. + 1 CD-ROM (4 3/4 in.)ISBN:
  • 9780387277288
  • 9780387289656
  • 0387277285 (alk. paper)
Subject(s): DDC classification:
  • 621.395
LOC classification:
  • H36 2006
Online resources:
Contents:
Tutorial I: The 15 Minute Design -- The Altera UP 3 Board -- Programmable Logic Technology.-
Tutorial II: Sequential Design and Hierarchy -- UP3core Library Functions --Using VHDL for Synthesis of Digital Hardware -- Using Verilog for Synthesis of Digital Hardware -- State Machine Design: The Electric Train Controller -- A Simple Computer Design: The UP 3 -- VGA Video Display Generation -- Interfacing to the PS/2 Keyboard and Mouse -- Legacy Digital I/O Interfacing Standards -- UP3 Robotics Projects -- A RISC Design: Synthesis of the MIPS Processor Core -- Introducing System-on-a-Programmable Chip.
Tutorial III: NIOS II Processor Software Development.
Tutorial IV: NIOS II Processor Hardware Design.
Appendix A: Generation of Pseudo Random Binary Sequences.- Appendix B: Quartus II Design and Data File Extensions.- Appendix C: UP 3 Pin Assignments.- Appendix D: ASCII Character Code.- Appendix E: Programming the UP 3's Flash Memory.
Holdings
Item type Current library Call number Copy number Status Date due Barcode
General Lending Carlow Campus Library General Lending 621.395 (Browse shelf(Opens below)) 1 Available 49614
General Lending Carlow Campus Library General Lending 621.395 (Browse shelf(Opens below)) 1 Available 49615

Includes bibliographical references and index.

Tutorial I: The 15 Minute Design -- The Altera UP 3 Board -- Programmable Logic Technology.-

Tutorial II: Sequential Design and Hierarchy -- UP3core Library Functions --Using VHDL for Synthesis of Digital Hardware -- Using Verilog for Synthesis of Digital Hardware -- State Machine Design: The Electric Train Controller -- A Simple Computer Design: The UP 3 -- VGA Video Display Generation -- Interfacing to the PS/2 Keyboard and Mouse -- Legacy Digital I/O Interfacing Standards -- UP3 Robotics Projects -- A RISC Design: Synthesis of the MIPS Processor Core -- Introducing System-on-a-Programmable Chip.

Tutorial III: NIOS II Processor Software Development.

Tutorial IV: NIOS II Processor Hardware Design.

Appendix A: Generation of Pseudo Random Binary Sequences.- Appendix B: Quartus II Design and Data File Extensions.- Appendix C: UP 3 Pin Assignments.- Appendix D: ASCII Character Code.- Appendix E: Programming the UP 3's Flash Memory.

62.21

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