Logic design and verification using SystemVerilog / Donald Thomas.
Material type:![Text](/opac-tmpl/lib/famfamfam/BK.png)
- 1500385786
- 9781500385781
- 621.395
Item type | Current library | Call number | Copy number | Status | Date due | Barcode |
---|---|---|---|---|---|---|
General Lending | Carlow Campus Library General Lending | 621.395 (Browse shelf(Opens below)) | 1 | Available | 78336 |
Includes index.
Tutorial introduction -- Combinational logic -- Finite state machines -- The snychronous assumption -- Hardware threads (FSM-D) -- Interfacing -- Testbenches -- Concurrent testbenches -- Assertions and sequences -- Functional coverage -- Procedural models -- Structural models -- Arrays -- Simulation kernel.
The book assumes a basic background in logic design and software programming concepts. It is directed at students, designers who want to update their skills from Verilog or VHDL, and, to students in VLSI design and advanced logic design courses that include verification and design topics. The book starts with a tutorial introduction on hardware description languages and simulation, proceeds to the register-transfer design topics of combinational and finite state machine (FSM) design ; covers the design of FSM-datapath designs and their interfaces, including SystemVerilog interfaces ; then moves to the more advanced topics of writing testbenches including using assertions and functional coverage.--Paraphrased from distributor's web site.
69.99