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SystemVerilog for verification : a guide to learning the testbench language features / Chris Spear, Greg Tumbush.

By: Contributor(s): Material type: TextTextPublication details: New York : Springer, c2012.Edition: 3rd edDescription: xliii, 464 p. : ill. ; 24 cmISBN:
  • 9781461407140
  • 1461407141 (alk. paper)
  • 9781461407140 (alk. paper)
Other title:
  • System Verilog for verification
Subject(s): DDC classification:
  • 621.392
LOC classification:
  • .S67 2012
Contents:
Verification Guidelines -- Data Types -- Procedural Statements and Routines -- Connecting the Testbench and Design -- Basic OOP -- Randomization -- Threads and Interprocess Communication -- Advanced OOP and Testbench Guidelines -- Functional Coverage -- Advanced Interfaces -- A Complete SystemVerilog Testbench -- Interfacing with C/C++.
Holdings
Item type Current library Call number Status Date due Barcode
General Lending Carlow Campus Library General Lending 621.392 (Browse shelf(Opens below)) Checked out 27/08/2020 81075
General Lending Carlow Campus Library General Lending 621.392 (Browse shelf(Opens below)) Available 81076

CW558

CW527

Includes bibliographical references (p. 455) and index.

Verification Guidelines -- Data Types -- Procedural Statements and Routines -- Connecting the Testbench and Design -- Basic OOP -- Randomization -- Threads and Interprocess Communication -- Advanced OOP and Testbench Guidelines -- Functional Coverage -- Advanced Interfaces -- A Complete SystemVerilog Testbench -- Interfacing with C/C++.

58.52

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