Design for embedded image processing on FPGAs / Donald G. Bailey.
Material type:![Text](/opac-tmpl/lib/famfamfam/BK.png)
- 9780470828496:
- 0470828498
- 9780470828502 (electronic bk.)
- 0470828501 (electronic bk.)
- 9780470828519 (e-book)
- 047082851X (e-book)
- 621.399
- B3264 2011
IEEE ebook
IT Carlow ebook
Includes bibliographical references and index.
Design for Embedded Image Processing on FPGAs; Contents; Preface; Acknowledgements; 1 Image Processing; 1.1 Basic Definitions; 1.2 Image Formation; 1.3 Image Processing Operations; 1.4 Example Application; 1.5 Real-Time Image Processing; 1.6 Embedded Image Processing; 1.7 Serial Processing; 1.8 Parallelism; 1.9 Hardware Image Processing Systems; 2 Field Programmable Gate Arrays; 2.1 Programmable Logic; 2.1.1 FPGAs vs. ASICs; 2.2 FPGAs and Image Processing; 2.3 Inside an FPGA; 2.3.1 Logic; 2.3.2 Interconnect; 2.3.3 Input and Output; 2.3.4 Clocking; 2.3.5 Configuration; 2.3.6 Power Consumption
"The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation"-- Provided by publisher
"Introductory material will consider the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage will be given of a range of image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques will be illustrated with several example applications or case studies from projects or applications I have been involves with. Issues such as interfacing between the FPGA and peripheral devices will be covered briefly, as will designing the system in such a way that it can be more readily debugged and tuned"-- Provided by publisher
Description based on print version record.