| 000 | 01874cam a2200529 a 4500 | ||
|---|---|---|---|
| 001 | BDZ0005601724 | ||
| 003 | StDuBDS | ||
| 005 | 20190531160420.0 | ||
| 006 | m d | ||
| 008 | 040510s2004 enk 001 0 eng d | ||
| 020 |
_a9780471441489 : _c£50.50 |
||
| 020 | _a0471441481 (cloth) | ||
| 020 | _a9780471441489 (cloth) | ||
| 020 | _a0471723002 (electronic bk.) | ||
| 020 | _a9780471723004 (electronic bk.) | ||
| 035 | _a(OCoLC)85820224 | ||
| 040 |
_aIeDuTC _dUk _dStDuBDSZ |
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| 049 | _aTIZA | ||
| 072 | 7 |
_aTJF _2thema |
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| 072 | 7 |
_aUYD _2thema |
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| 072 | 7 |
_aTJ _2thema |
|
| 082 | _a621.392 | ||
| 100 | 1 | _aPatmaṉāpaṉ, Ṭi. Ār. | |
| 245 | 1 | 0 |
_aDesign through Verilog HDL / _cT.R. Padmanabhan, B. Bala Tripura Sundari. |
| 260 |
_aNew York ; _aChichester : _bWiley, _cc2004. |
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| 300 |
_axii, 455 p. ; _c24 cm. |
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| 500 | _aIT Carlow ebook | ||
| 500 | _aIEEE ebook | ||
| 504 | _aIncludes bibliographical references and index. | ||
| 650 | 0 | _aVerilog (Computer hardware description language) | |
| 650 | 7 |
_aElectronics engineering _2thema |
|
| 650 | 7 |
_aSystems analysis & design _2thema |
|
| 650 | 7 |
_aElectronics & communications engineering _2thema |
|
| 653 | _aElectrical and Electronics Engineering. | ||
| 700 | 1 | _aTripura Sundari, B. Bala. | |
| 710 | 2 | _aJohn Wiley & Sons. | |
| 776 | 1 |
_cOriginal _z0471441481 _w(DLC) 2003057671 |
|
| 856 | 4 | 0 |
_yRead this electronic book via the web _uhttp://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5236707 |
| 856 | 4 | 1 |
_ySend a message to library staff if access to this online resource is unavailable _umailto:libdesk@itcarlow.ie?subject=Resource%20unavailable |
| 902 | _a160105 | ||
| 907 |
_a.b10373366 _bnone _c- |
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