000			02158cam a2200337Ii 4500
008			150716s2015 000 0 eng d
020			_a1500385786
020			_a9781500385781
035			_a(OCoLC)903912234
040			_aMNU _beng _erda _cMNU _dOCLCF
082			_a621.395
100	1		_aThomas, D. E. _q(Donald E.), _d1951-
245	1	0	_aLogic design and verification using SystemVerilog / _cDonald Thomas.
264		1	_a[Lexington, Kentucky] : _bCreateSpace, _c[2014]
264		3	_aLexington, KY : _bCreateSpace, _c2014.
264		4	_c©2014
300			_axxii, 303 pages : _billustrations ; _c25 cm ; _epbk.
336			_btxt
337			_bn
338			_bnc
500			_aIncludes index.
505	0		_aTutorial introduction -- Combinational logic -- Finite state machines -- The snychronous assumption -- Hardware threads (FSM-D) -- Interfacing -- Testbenches -- Concurrent testbenches -- Assertions and sequences -- Functional coverage -- Procedural models -- Structural models -- Arrays -- Simulation kernel.
520			_aThe book assumes a basic background in logic design and software programming concepts. It is directed at students, designers who want to update their skills from Verilog or VHDL, and, to students in VLSI design and advanced logic design courses that include verification and design topics. The book starts with a tutorial introduction on hardware description languages and simulation, proceeds to the register-transfer design topics of combinational and finite state machine (FSM) design ; covers the design of FSM-datapath designs and their interfaces, including SystemVerilog interfaces ; then moves to the more advanced topics of writing testbenches including using assertions and functional coverage.--Paraphrased from distributor's web site.
590			_a69.99
650		0	_aSystemVerilog (Computer hardware description language)
650		0	_aElectronic circuits. _93240
902			_a161122
907			_a.b10469321 _bcgen _c-
942			_n0
998			_b0 _c150716 _dm _ea _f- _g0
999			_c44816 _d44816