Writing testbenches : functional verification of HDL models / by Janick Bergeron.

By:

Bergeron, Janick

Material type: Text

TextPublication details: Boston, [Mass.] ; London : Kluwer Academic, [2003?]Edition: 2nd edDescription: xxx, 475 p. : ill. ; 25 cmISBN:

9781402074011 :
1402074018

Subject(s):

DDC classification:

621.392

Online resources:

Contents:

What is Verification? -- Verification tools -- The verification plan -- High level modeling -- Stimulus and response -- Architects testbenches -- Simulation management

Holdings ( 1 )
Title notes ( 3 )

Holdings
Item type	Current library	Call number	Copy number	Status	Date due	Barcode
General Lending	Carlow Campus Library General Lending	621.392 (Browse shelf(Opens below))	1	Available		59175

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Previous	621.392 The quintessential PIC microcontroller /	621.392 Embedded system design on a shoestring : achieving high performance with a limited budget /	621.392 Computers as components : principles of embedded computing system design /	621.392 Writing testbenches : functional verification of HDL models /	621.392 RTL hardware design using VHDL : coding for efficiency, portability, and scalability /	621.392 Embedded systems. Volume 3, Real-time operating systems for the ARM Cortex-M3 /	621.392 Embedded systems. Volume 3, Real-time operating systems for the ARM Cortex-M3 /	Next

CW508

What is Verification? -- Verification tools -- The verification plan -- High level modeling -- Stimulus and response -- Architects testbenches -- Simulation management

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