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Reconfigurable computing : the theory and practice of FPGA-based computation / edited by Scott Hauck and André DeHon.

Contributor(s): Material type: TextTextSeries: Systems on siliconPublication details: Amsterdam ; London : Morgan Kaufmann, 2008.Description: xxix, 908 p. : ill. ; 24 cmISBN:
  • 9780123705228:
  • 0123705223
Subject(s): DDC classification:
  • 621.395
LOC classification:
  • R43 2008
Contents:
[Part One: Reconfigurable Computing Hardware] Chapter 1 - Device Architecture -- Chapter 2 - Reconfigurable Computing Devices -- Chapter 3 - Reconfigurable Computing Systems -- Chapter 4 - Reconfiguration Management
[Part Two: Software] Part II Intro -- Chapter 5 - Computer Models and System Architectures André DeHon -- Chapter 6 - Hardware Description Languages (VHDL) -- Chapter 7 - Compilation for Reconfigurable Computing Machines -- Chapter 8 - Streaming Models 8.1 MATLAB/SIMULINK 8.2 SCORE -- Chapter 9 SIMD/Vector -- Chapter 10 - OS/Runtime Systems -- Chapter 11 - JHDL -- Chapter 12 -Technology Mapping -- Chapter 13 - Placement 13.1 General-purpose / FPGA 13.2 Datapath 13.3 Constructive -- Chapter 14 - Routing -- Chapter 15 - Retimin -- Chapter 16 - Bitstream Generation, JBits -- Chapter 17 - Fast Mapping
[Part Three: Application Development] PART III INTRO -- Chapter 18 - Evaluating and Optimizing problems for FPGA implementations -- Chapter 19- Instance-specific design, Constant Propagation & Partial Evaluation -- Chapter 20 - Precision Analysis & Floating Point -- Chapter 21 - Distributed Arithmetic -- Chapter 22 - CORDIC -- Chapter 23 - Task allocation: FPGA vs. CPU partitioning
[PART Four: Case Studies] Chapter 24 - Image Processing, Variable Precision, Algorithm Alteration: SPIHT Compression -- Chapter 25 - Run-time reconfiguration: Automatic Target Recognition -- Chapter 26 - Problem-specific circuitry: SAT Solving -- Chapter 27 - Multi-FPGA Systems: Logic Emulation -- Chapter 28- Floating Point -- Chapter 29 - FDTD -- Chapter 30 - Genetic Evolution -- Chapter 31 - Packet Filtering (Networking application) -- Chapter 32 - Active Pages [Memory centric]
[Part Five: Theoretical Underpinnings and Future Directions] PART V INTRO Chapter 33- Theoretical Underpinnings, Metrics and Analysis -- Chapter 34 - Defect and Fault Tolerance -- Chapter 35 - Reconfigurable Computing and Nanotechnology
Holdings
Item type Current library Call number Copy number Status Date due Barcode
General Lending Carlow Campus Library General Lending 621.395 (Browse shelf(Opens below)) 1 Available 57021

Includes bibliographical references and index.

[Part One: Reconfigurable Computing Hardware] Chapter 1 - Device Architecture -- Chapter 2 - Reconfigurable Computing Devices -- Chapter 3 - Reconfigurable Computing Systems -- Chapter 4 - Reconfiguration Management

[Part Two: Software] Part II Intro -- Chapter 5 - Computer Models and System Architectures André DeHon -- Chapter 6 - Hardware Description Languages (VHDL) -- Chapter 7 - Compilation for Reconfigurable Computing Machines -- Chapter 8 - Streaming Models 8.1 MATLAB/SIMULINK 8.2 SCORE -- Chapter 9 SIMD/Vector -- Chapter 10 - OS/Runtime Systems -- Chapter 11 - JHDL -- Chapter 12 -Technology Mapping -- Chapter 13 - Placement 13.1 General-purpose / FPGA 13.2 Datapath 13.3 Constructive -- Chapter 14 - Routing -- Chapter 15 - Retimin -- Chapter 16 - Bitstream Generation, JBits -- Chapter 17 - Fast Mapping

[Part Three: Application Development] PART III INTRO -- Chapter 18 - Evaluating and Optimizing problems for FPGA implementations -- Chapter 19- Instance-specific design, Constant Propagation & Partial Evaluation -- Chapter 20 - Precision Analysis & Floating Point -- Chapter 21 - Distributed Arithmetic -- Chapter 22 - CORDIC -- Chapter 23 - Task allocation: FPGA vs. CPU partitioning

[PART Four: Case Studies] Chapter 24 - Image Processing, Variable Precision, Algorithm Alteration: SPIHT Compression -- Chapter 25 - Run-time reconfiguration: Automatic Target Recognition -- Chapter 26 - Problem-specific circuitry: SAT Solving -- Chapter 27 - Multi-FPGA Systems: Logic Emulation -- Chapter 28- Floating Point -- Chapter 29 - FDTD -- Chapter 30 - Genetic Evolution -- Chapter 31 - Packet Filtering (Networking application) -- Chapter 32 - Active Pages [Memory centric]

[Part Five: Theoretical Underpinnings and Future Directions] PART V INTRO Chapter 33- Theoretical Underpinnings, Metrics and Analysis -- Chapter 34 - Defect and Fault Tolerance -- Chapter 35 - Reconfigurable Computing and Nanotechnology

58.49

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